The present disclosures relate to electrostatic discharge protection, and more particularly, to an ESD protection circuit with an isolated diode element and method thereof.
Electrostatic Discharge (ESD) events are high electrical potentials with limited energy that can damage the gate oxides of Field Effect Transistors (FET), by forcing currents to flow through the oxides resulting in a weakened oxide, or reaching sufficient potential to rupture the oxide resulting in a gate short (low resistance path) to another device terminal. ESD events can be caused by human body or machines such as wafer saw.
An ESD protection circuit is comprised of a positive turn-on voltage clamp and a negative turn-on voltage clamp. The positive turn-on voltage clamp design should take into consideration the voltage swing of the signal. It must be designed to sink ESD current at a preset voltage. In most ESD protection circuits, while the design of the positive turn-on voltage clamp requires great attention, the negative turn-on voltage clamp is only designed to sink ESD current at any voltage before device breakdown. Typically, the negative turn-on voltage clamp simply uses a forward diode.
Among various RF circuits, power amplifiers have stringent requirements in both ESD protection and RF performance. In addition, a problem in the art exists with junction isolated ESD circuits in that a junction isolated ESD circuit is subject to ‘turn on’ when the circuit experiences bias conditions of opposite polarity from its intended normal operating conditions. For radio frequency (RF) field-effect transistors (FETs), such a condition can occur on the gates of the RF FETs (relative to the body) depending upon the drive levels and the class of operation. When the ESD circuit turns on, it can interact with the input signal and bias circuitry, resulting in distortion of the input signal and poor RF performance.
Prior solutions include use of diodes for ESD circuits that are generally fabricated in the single crystal portion of the semiconductor substrate. In addition, isolation provided and used by such diodes is not intended to resolve issue of opposite bias polarity. Furthermore, isolated poly diodes have been used as fuses for programmable cross point arrays, such as in U.S. Pat. No. 6,670,824 B2. Isolated poly diodes have also been used for input drive protection, as disclosed in U.S. Pat. No. 5,139,959A. However, isolated poly diodes have not been known to be related to an ESD circuit element to address the problems as discussed herein.
FIG. 1 is a schematic representation view 10 of a standard ESD circuit and protected device, as is known in the art. Problems occur with respect to conduction of standard grounded gate n-type Laterally Diffused Metal Oxide Semiconductor (LDMOS) ggNMOSFET ESD circuits during −Vgs conditions (i.e., negative Vgs voltage conditions). The ESD circuit 14 is formed with a common source with the protected device 12. During operation, a −Vgs on the gate of the main FET 12 is a −Vds on the ggNMOSFET ESD circuit 14 and undesirably forward biases the drain-source junction of ESD circuit 14. Protected device 12 includes, for example, an RF LDMOS FET or other transistor device. For an RF amplifier application, the input can include, for example, a DC bias coupled with an RF signal on top of the DC bias.
Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.
The use of the same reference symbols in different drawings indicates similar or identical items. Skilled artisans will also appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.